The present invention relates to a low power dissipation crystal oscillator, and more particularly to an oscillator employing complementary insulated gate (e.g. Metal-Oxide-Semiconductor) field-effect transistors (CMOS FET).
In general, a crystal oscillator used in a crystal watch essentially consists of an inverter circuit including CMOS FET and an excitation circuit including a crystal resonator. In operation, the feedback of the output of the CMOS inverter, provided that the bias point is set in a linear region of transfer characteristics of the CMOS inverter enables the crystal resonator to be excited. Using CMOS FETs in a crystal oscillator makes it possible to remarkably lessen power dissipation.
Power dissipation P is, in general, expressed by the following equation (1). EQU P = P.sub.Q + P.sub.dyn + P.sub.s ( 1)
where P.sub.Q is power dissipation in a static condition due, for example, to leak current of usually negligible value, of the order magnitude of nA (nano amperes) at a normal temperature, P.sub.dyn is the power dissipation in an operational condition and is expressed by the following expression; EQU P.sub.dyn .alpha.C V.sub.D.sup.2 f.sub.o
where C is a capacitive load, V.sub.D is a supply voltage, and f.sub.o is an oscillating frequency. Further, in the above eq. (1), P.sub.s is the power dissipation in a switching transition state. Although the value of P.sub.s is relatively small, it must take into account the power dissipation P.sub.s in a crystal oscillator used in a liner (unsaturated) region of the transfer characteristics of the CMOS inverter.
Improvements in high power batteries which have been assembled in crystal watches have proceeded rapidly. Batteries having 150 mAH, and a life of about two years have been obtained. However, it is impossible to completely guarantee for a long time the power dissipation in a crystal oscillator. For this reason, reduction of the power dissipation as shown in eq. (1) is greatly desired.
As a result of study and experiments on CMOS circuits, I have invented a novel crystal oscillator in which the power dissipation can be extremely reduced by respectively applying different DC bias potentials to each gate of CMOS FETs.